Lead Engineer/ Senior Engineer, Analog Layout Design

The Hong Kong Applied Science and Technology Research Institute (ASTRI) was founded by the Government of the Hong Kong Special Administrative Region in 2000 with the mission of enhancing Hong Kong’s competitiveness through applied research. ASTRI’s core R&D competence in various areas is grouped under five Technology Divisions: Communications Technologies, Artificial Intelligence and Trust Technologies, Advanced Electronic Components and Systems, IoT Sensing and AI Technologies, and Innovative Mind.

It is applied across six core areas which are Smart City, Financial Technologies, New Industrialisation and Intelligent Manufacturing, Digital Health, Application Specific Integrated Circuits, and Metaverse.

Over the years, ASTRI has nurtured a pool of research, I&T talents and received numerous international awards for its pioneering innovations as well as outstanding business and community contributions. To date, ASTRI has transferred almost 1500 technologies to the industries and been granted more than 1100 patents in the Mainland, the US, and other countries.

To support our constant endeavour to position Hong Kong as a world-class smart city and an international hub of innovation and technology, we are seeking qualified professionals to fill the following position(s):

​​​​Job Responsibilities:

• Engage in layout design, structures, and reviews processes for assigned projects
• Lead the layout implementation and physical verification to meet schedule and quality targets
• Prepare technical reports, presentations, and design documentation for projects
• Act as the technical interface with foundries on layout-related queries and technology files
• Perform ad hoc duties as assigned

Job Requirements:

• Bachelor's degree or above in Electronic Engineering or related fields with 5+ years relevant experience
• Candidate with less experience may also be considered
• Strong experience in analog layout design, especially in ADC, DAC, PMU, SerDes, MIPI, and PCIe
• Strong background in mixed signal IC design such as GPIO, LVDS and RGMII IO will be a plus
• Good experiences in Cadence Liberate, Abstract, Virtuoso, and MMSIM will be a plus
• Good communication and interpersonal skills, a good team work player
• Lives ASTRI values

For interested parties, please submit your application with detailed CV within two weeks of the post date. Applicants are encouraged to submit their applications as soon as possible. The review of applications will continue until post is filled.

The appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work a five-day week.

The resume should not include any sensitive personal information such as HKID or passport number, photo, etc.

Position offer is subject to the applicant’s experience and academic qualification. Only short-listed candidates will be notified. ASTRI reserves the right not to fill the position.

ASTRI is an Equal Opportunities Employer. Personal data provided by job applicants will be used exclusively for recruitment only. For details, please refer to ASTRI Privacy Policy Statement.